The present disclosure relates to solid-state imaging devices, imaging systems, and method for driving solid-state imaging devices having sensing elements for measuring physical quantities with respect to visible rays, electromagnetic waves, alpha rays, beta rays, etc.
In addition to sensors using charge-coupled devices (CCDs) (hereinafter referred to as “CCD sensors”) which prevailed in image sensors, image sensors using metal oxide semiconductors (MOSs) (hereinafter referred to as “MOS sensors”) which are fabricated using a standard process used for logic large scale integrated circuits (LSIs) have been widely distributed in the market today. Unlike CCD sensors, a MOS sensor allows a variety of analog and digital circuits to be integrated on a same substrate with a pixel array. A CCD sensor can generate a digital output signal only after the pixel array is coupled with an individual chip having an analog-to-digital (hereinafter “AD”) conversion function, such as an analog front-end processor (hereinafter “AFE”) specialized for an analog signal amplification function and an AD conversion function, or a digital signal processor (hereinafter “DSP”) having an AFE function. In contrast, MOS sensors in which a pixel array and an AD conversion circuit (hereinafter “ADC”) are integrated on a same chip are already commercially available.
Various conversion techniques have been proposed for ADCs installed in MOS sensors, including a pipeline AD conversion technique, which is widely used in AFEs, a column-parallel AD conversion technique, which performs an AD conversion operation on a line of pixel data concurrently and in parallel, and a technique which performs an AD conversion operation on all the pixel data concurrently and in parallel.
There is also a demand for such ADCs to operate at a higher speed and with higher accuracy. One example of achieving a higher speed and higher accuracy is a solid-state imaging device installed in an imaging device such as a digital camera, in which a ramp ADC for converting an analog pixel signal into a digital signal is provided in every one or more pixel columns, a column counter provided in each of the ramp ADCs stores upper bits of the digital signal, and a clock signal is supplied to a latch so that lower bits are stored therein, thereby achieving high-speed, high accuracy AD conversion while preventing an increase of clock frequency (see, e.g., Japanese Patent Publication No. 2009-038726 (Patent Document 1)).